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1 ltc1159/ltc1159 - 3. 3/ltc1159 - 5 s f ea t u re d u escriptio n operation from 4v to 40v input voltage n ultra-high efficiency: up to 95% n 20 m a supply current in shutdown n high efficiency maintained over wide current range n current mode operation for excellent line and load transient response n very low dropout operation: 100% duty cycle n short-circuit protection n synchronous fet switching for high efficiency n adaptive non-overlap gate drives n available in ssop and so packages the ltc ? 1159 series is a family of synchronous step-down switching regulator controllers featuring automatic burst mode tm operation to maintain high efficiencies at low output currents. these devices drive external complemen- tary power mosfets at switching frequencies up to 250khz using a constant off-time current-mode architecture. a separate pin and on-board switch allow the mosfet driver power to be derived from the regulated output voltage providing significant efficiency improvement when operating at high input voltages. the constant off-time current-mode architecture maintains constant ripple cur- rent in the inductor and provides excellent line and load transient response. the output current level is user pro- grammable via an external current sense resistor. the ltc1159 automatically switches to power saving burst mode operation when load current drops below approximately 15% of maximum current. standby current is only 300 m a while still regulating the output and shut- down current is a low 20 m a. high efficiency synchronous step-down switching regulators n step-down and inverting regulators n notebook and palmtop computers n portable instruments n battery-operated digital devices n industrial power distribution n avionics systems n telecom power supplies u s a o pp l ic at i figure 1. high efficiency step-down regulator load current (a) 0.02 60 efficiency (%) 70 80 100 0.2 2 ltc1159 ?ta01 90 v in = 10v v in = 20v figure 1 circuit ltc1159-5 efficiency 0.15 m f v in cap p-drive extv cc ltc1159-5 shdn1 i th c t s-gnd p-gate v cc v cc shdn2 sense sense + p-gnd n-gate 0.01 m f si9410dy 0.1 m f 1n4148 v in si9435dy d1 mbrs140t3 l* 33 m h r sense 0.05 w v out 5v/2a + c out 220 m f + c in 100 m f 100v + 3.3 m f 0v = normal >2v = shutdown 3300pf c t 300pf 1k ltc1159 ?f01 *coiltronics ctx33-4-mp u a o pp l ic at i ty p i ca l burst mode is a trademark of linear technology corporation. , ltc and lt are registered trademarks of linear technology corporation.
2 ltc1159/ltc1159-3.3/ltc1159-5 symbol parameter conditions min typ max units v fb feedback voltage (ltc1159 only) l 1.21 1.25 1.29 v i fb feedback current (ltc1159 only) l 0.2 m a v out regulated output voltage v in = 9v ltc1159-3.3 i load = 700ma l 3.23 3.33 3.43 v ltc1159-5 i load = 700ma l 4.90 5.05 5.20 v d v out output voltage line regulation v in = 9v to 40v C 40 0 40 mv output voltage load regulation ltc1159-3.3 5ma < i load < 2a l 40 65 mv ltc1159-5 5ma < i load < 2a l 60 100 mv burst mode output ripple i load = 0a 50 mv p-p i in v in pin current (note 3) normal mode v in = 12v, extv cc = 5v 200 m a v in = 40v, extv cc = 5v 300 m a shutdown v in = 12v, v shdn2 = 2v 15 m a v in = 40v, v shdn2 = 2v 25 m a i extvcc extv cc pin current (note 3) extv cc = 5v, sleep mode 250 m a v cc internal regulator voltage v in = 12v to 40v, extv cc = 0v, i cc = 10ma l 4.25 4.5 4.75 v v in C v cc v cc dropout voltage v in = 4v, extv cc = open, i cc = 10ma 300 400 mv a u g w a w u w a r b s o lu t exi t i s input supply voltage (pin 2)...................... C 15v to 60v v cc output current (pin 3) .................................. 50ma continuous pin currents (any pin) ...................... 50ma sense voltages ......................................... C 0.3v to 13v shutdown voltages ................................................... 7v extv cc input voltage ............................................. 15v operating temperature range .................... 0 c to 70 c extended commercial temperature range ............................... C 40 c to 85 c junction temperature (note 1) ............................ 125 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c wu u package / o rder i for atio ltc1159cg ltc1159cg-3.3 ltc1159cg-5 order part number t jmax = 125 c, q ja = 135 c/ w ltc1159cn ltc1159cn-3.3 ltc1159cn-5 ltc1159cs ltc1159cs-3.3 ltc1159cs-5 order part number 1 2 3 4 5 6 7 8 9 10 top view g package 20-lead plastic ssop 20 19 18 17 16 15 14 13 12 11 p-gate v in v cc p-drive p-drive v cc v cc c t i th sense cap shdn2 extv cc p-gnd n-gate p-gnd s-gnd shdn1 v fb sense + consult factory for industrial and military grade parts. e lectr ic al c c hara terist ics t a = 25 c, v in = 12v, v shdn1 = 0v (note 2), unless otherwise noted. 1 2 3 4 5 6 7 8 top view s package 16-lead plastic so n package 16-lead pdip 16 15 14 13 12 11 10 9 p-gate v in v cc p-drive v cc c t i th sense cap shdn2 extv cc n-gate p-gnd s-gnd sense + *fixed output versions v fb (shdn1)* t jmax = 125 c, q ja = 80 c/ w (n) t jmax = 125 c, q ja = 110 c/ w (s)
3 ltc1159/ltc1159 - 3. 3/ltc1159 - 5 symbol parameter conditions min typ max units v ext C v cc extv cc switch drop v in = 12v, extv cc = 5v, i switch = 10ma 250 350 mv v p-gate C v in p-gate to source voltage (off) v in = 12v C 0.2 0 v v in = 40v C 0.2 0 v v sense + C current sense threshold voltage v sense C ltc1159 v sense C = 5v, v fb = 1.32v (forced) 25 mv v sense C = 5v, v fb = 1.15v (forced) l 130 150 170 mv ltc1159-3.3 v sense C = 3.4v (forced) 25 mv v sense C = 3.1v (forced) l 130 150 170 mv ltc1159-5 v sense C = 5.2v (forced) 25 mv v sense C = 4.7v (forced) l 130 150 170 mv v sndn1 shdn1 threshold ltc1159cg, ltc1159-3.3, ltc1159-5 0.6 0.8 2 v v shdn2 shdn2 threshold 0.8 1.4 2 v i shdn2 shutdown 2 input current v shdn2 = 5v 12 20 m a i ct c t pin discharge current v out in regulation 50 70 90 m a v out = 0v 2 10 m a t off off-time (note 4) c t = 390pf, i load = 700ma, v in = 10v 4 5 6 m s t r , t f driver output transition times c l = 3000pf (pins p-drive and n-gate), v in = 6v 100 200 ns e lectr ic al c c hara terist ics t a = 25 c, v in = 12v, v shdn1 = 0v (note 2), unless otherwise noted. symbol parameter conditions min typ max units v fb feedback voltage (ltc1159 only) 1.2 1.25 1.3 v v out regulated output voltage v in = 9v ltc1159-3.3 i load = 700ma 3.17 3.30 3.43 v ltc1159-5 i load = 700ma 4.85 5.05 5.25 v i in v in pin current (note 3) normal v in = 12v, extv cc = 5v 200 m a v in = 40v, extv cc = 5v 300 m a shutdown v in = 12v, v shdn2 = 2v 15 m a v in = 40v, v shdn2 = 2v 25 m a i extvcc extv cc pin current (note 3) extv cc = 5v, sleep mode 250 m a v cc internal regulator voltage v in = 12v to 40v, extv cc = 0v, i cc = 10ma 4.5 v v sense + C current sense threshold voltage low threshold (forced) 25 mv v sense C high threshold (forced) 125 150 175 mv v shdn2 shdn2 threshold 0.8 1.4 2 v t off off-time (note 4) c t = 390pf, i load = 700ma, v in = 10v 3.5 5 6.5 m s C40 c t a 85 c (note 5) the l denotes specifications which apply over the full operating temperature range. note 1: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: ltc1159cg, ltc1159cg-3.3, ltc1159cg-5: t j = t a + (p d 135 c/w) ltc1159cn, ltc1159cn-3.3, ltc1159cn-5: t j = t a + (p d 80 c/w) ltc1159cs, ltc1159cs-3.3, ltc1159cs-5: t j = t a + (p d 110 c/w) note 2: on ltc1159 versions which have a shdn1 pin, it must be at ground potential for testing. note 3: the ltc1159 v in and extv cc current measurements exclude mosfet driver currents. when v cc power is derived from the output via extv cc , the input current increases by (i gatechg duty cycle)/(efficiency). see typical performance characteristics and applications information. note 4: in applications where r sense is placed at ground potential, the off- time increases approximately 40%. note 5: the ltc1159, ltc1159-3.3, and ltc1159-5 are not tested and not quality assurance sampled at C 40 c and 85 c. these specifications are guaranteed by design and/or correlation. note 6: the logic-level power mosfets shown in figure 1 are rated for v ds(max) = 30v. for operation at v in > 30v, use standard threshold mosfets with extv cc powered from a 12v supply. see applications information.
4 ltc1159/ltc1159-3.3/ltc1159-5 cc hara terist ics uw a t y p i ca lper f o r c e load regulation efficiency vs input voltage line regulation operating frequency vs (v in C v out ) extv cc switch drop current sense threshold voltage extv cc pin current v in pin current off-time vs v out input voltage (v) 0 80 efficiency (%) 85 90 95 100 5101520 ltc1159 ?tpc01 25 30 35 40 figure 1 circuit i load = 1a note 6 load current (a) 0 100 d v out (mv) ?0 ?0 ?0 ?0 0 20 0.5 1.0 1.5 2.0 ltc1159 ?tpc03 2.5 figure 1 circuit v in = 24v input voltage (v) 0 extv cc current (ma) 6 8 10 15 25 40 ltc1159 ?tpc04 4 2 0 510 20 30 35 figure 1 circuit note 6 i load = 1a i load = 100ma i load = 0 input voltage (v) 0 supply current ( m a) 300 400 500 15 25 40 ltc1159 ?tpc05 200 100 0 510 20 30 35 figure 1 circuit note 6 normal v shdn2 = 2v (v in ?v out ) voltage (v) 0 normalized frequency 1.0 1.5 20 ltc1159 ?tpc06 0.5 0 5 10 15 25 2.0 v out = 5v t = 70? t = 0? t = 25? switch current (ma) 0 0 extv cc ?v cc (mv) 100 200 300 400 500 600 5101520 ltc1159 ?tpc07 output voltage (v) 1 off-time ( m s) 40 50 60 5 ltc1159 ?tpc08 30 20 0 2 34 10 80 70 0 ltc1159-5 ltc1159-3.3 temperature (?) 20 sense voltage (mv) 80 100 120 100 ltc1159 ?tpc09 60 40 0 40 60 80 20 160 140 0 maximum threshold minimum threshold input voltage (v) 0 ?0 d v out (mv) ?0 ?0 0 20 10 20 30 40 lt1159 ?tpc02 40 60 515 25 35 figure 1 circuit i load = 1a note 6
5 ltc1159/ltc1159 - 3. 3/ltc1159 - 5 pi fu ctio s u uu sense + : the (+) input for the current comparator. a built- in offset between the sense + and sense C pins, in conjunc- tion with r sense , sets the current trip threshold. n-gate: high current drive for the bottom n-channel mosfet. the n-gate pin swings from ground to v cc . p-gate: level-shifted gate drive signal for the top p-channel mosfet. the voltage swing at the p-gate pin is from v in to v in C v cc . p-drive: high current gate drive for the top p-channel mosfet. the p-drive pin(s) swing(s) from v cc to ground. cap: charge compensation pin. a capacitor to v cc pro- vides charge required by the p-gate level-shift capacitor during supply transitions. the charge compensation ca- pacitor must be larger than the gate drive capacitor . shdn1: this pin shuts down the control circuitry only (v cc is not affected). taking shdn1 pin high turns off the control circuitry and holds both mosfets off. this pin must be at ground potential for normal operation. shdn2: master shutdown pin. taking shdn2 high shuts down v cc and all control circuitry. the ltc1159 uses a current mode, constant off-time architecture to synchronously switch an external pair of complementary power mosfets. operating frequency is set by an external capacitor at the c t pin. the output voltage is sensed either by an internal voltage divider connected to the sense C pin (ltc1159-3.3 and ltc1159-5) or an external divider returned to the v fb pin (ltc1159). a voltage comparator v, and a gain block g, compare the divided output voltage with a reference voltage of 1.25v. to optimize efficiency, the ltc1159 automatically switches between two modes of operation, burst and continuous. a low dropout 4.5v regulator provides the operating volt- age v cc for the mosfet drivers and control circuitry during start-up. during normal operation, the ltc1159 family powers the drivers and control from the output via the extv cc pin to improve efficiency. the n-gate pin is referenced to ground and drives the n-channel mosfet (refer to functional diagram) gate directly. the p-channel gate drive must be referenced to the main supply input v in , which is accomplished by level-shifting the p-drive signal via an internal 550k resis- tor and external capacitor. during the switch on cycle in continuous mode, current comparator c monitors the voltage between the sense + and sense C pins connected across an external shunt in series with the inductor. when the voltage across the shunt reaches its threshold value, the p-gate output is switched to v in , turning off the p-channel mosfet. the timing capacitor c t is now allowed to discharge at a rate determined by the off-time controller. the discharge current is made proportional to the output voltage to model the inductor current, which decays at a rate which is also proportional to the output voltage. while the timing capacitor is discharging, the n-gate output is high, turning on the n-channel mosfet. operatio u v in : main supply input pin. s-gnd: small signal ground. must be routed separately from other grounds to the (C) terminal of c out . p-gnd: driver power grounds. connect to source of n- channel mosfet and the (C) terminal of c in . v cc : outputs of internal 4.5v linear regulator, extv cc switch, and supply inputs for driver and control circuits. the driver and control circuits are powered from the higher of the 4.5v regulator or extv cc voltage. must be closely decoupled to power ground. c t : external capacitor c t from this pin to ground sets the operating frequency. (the frequency is also dependent on the ratio v out /v in .) i th : gain amplifier decoupling point. the current com- parator threshold increases with the i th pin voltage. v fb : for the ltc1159 adjustable version, the v fb pin receives the feedback voltage from an external resistive divider used to set the output voltage. sense C : connects to internal resistive divider which sets the output voltage in fixed output versions. the sense C pin is also the (C) input of the current comparator.
6 ltc1159/ltc1159-3.3/ltc1159-5 when the voltage on c t has discharged past v th1 , com- parator t trips, setting the flip-flop. this causes the n-gate output to go low (turning off the n-channel mosfet) and the p-gate output to also go low (turning the p-channel mosfet back on). the cycle then repeats. as the load current increases, the output voltage decreases slightly. this causes the output of the gain stage to increase the current comparator threshold, thus tracking the load current. the sequence of events for burst mode operation is very similar to continuous operation with the cycle interrupted by the voltage comparator. when the output voltage is at or above the desired regulated value, the p-channel mosfet is held off by comparator v and the timing capacitor continues to discharge below v th1 . when the timing capacitor discharges past v th2 , voltage comparator s trips, causing the internal sleep line to go low and the n-channel mosfet to turn off. the circuit now enters sleep mode with both power mosfets turned off. in sleep mode, much of the cir- cuitry is turned off, dropping the supply current from several milliamps (with the mosfets switching) to 300 m a. when the output capacitor has discharged by the amount of hysteresis in comparator v, the p-channel mosfet is again turned on and this process repeats. to avoid the operation of the current loop interfering with burst mode operation, a built-in offset is incorporated in the gain stage. to prevent both the external mosfets from being turned on at the same time, feedback is incorporated to sense the state of the driver output pins. before the n-gate output can go high, the p-drive output must also be high. likewise, the p-drive output is prevented from going low when the n- gate output is high. operatio u (refer to functional diagram) internal divider broken at v fb for adjustable versions. fu ctio al diagra u uw + n-gate p-drive v cc 550k p-gate p-gnd 550k cap low drop switch v cc extv cc shdn2 v in + + sense + v r s q v th1 + 25mv to 150mv 13k g reference 1.25v s-gnd i th c v os sense ltc1159 ?fd shdn1 + t v th2 s sleep c t v fb off-time control sense low dropout 4.5v regulator 100k
7 ltc1159/ltc1159 - 3. 3/ltc1159 - 5 applicatio s i for atio w uu u both track i max . once r sense has been chosen, i burst and i sc(pk) can be predicted from the following equations: i burst ? 15mv r sense i sc(pk) = 150mv r sense the ltc1159 automatically extends t off during a short circuit to allow sufficient time for the inductor current to decay between switch cycles. the resulting ripple current causes the average short-circuit current i sc(avg) to be reduced to approximately i max . the ltc1159 compared to the ltc1148/ltc1149 families the ltc1159 family is closest in operation to the ltc1149 and shares much of the applications information. in addi- tion to reduced quiescent and shutdown currents, the ltc1159 adds an internal switch which allows the driver and control sections to be powered from an external source for higher efficiency. this change affects power mosfet selection, extv cc pin connection, important information about ltc1159 adjustable applications, and efficiency considerations found in this section. the basic ltc1159 application circuit shown in figure 1 is limited to a maximum input voltage of 30v due to mosfet breakdown. if the application does not require greater than 18v operation, then the ltc1148 or ltc1148hv should be used. for higher input voltages where quiescent and shutdown current are not critical, the ltc1149 may be a better choice since it is set up to drive standard threshold mosfets. r sense selection for output current r sense is chosen based on the required output current. the ltc1159 current comparator has a threshold range which extends from a minimum of 0.025v/r sense to a maximum of 0.15v/r sense . the current comparator threshold sets the peak of the inductor ripple current, yielding a maximum output current i max equal to the peak value less half the peak-to-peak ripple current. for proper burst mode opera- tion, i ripple(p-p) must be less than or equal to the minimum current comparator threshold. since efficiency generally increases with ripple current, the maximum allowable ripple current is assumed, i.e., i ripple(p-p) = 0.025v/r sense (see c t and l selection for operating frequency). solving for r sense and allowing a margin for variations in the ltc1159 and external component values yields: r sense = m w 100 i max a graph for selecting r sense versus maximum output current is given in figure 2. the ltc1159 series works well with values of r sense from 0.02 w to 0.2 w . the load current below which burst mode operation com- mences, i burst , and the peak short-circuit current, i sc(pk) , l and c t selection for operating frequency the ltc1159 uses a constant off-time architecture with t off determined by an external timing capacitor c t . the value of c t is calculated from the desired continuous mode operating frequency, f: c t = 7.8 10 ? f ) ) 1 ? v out v in a graph for selecting c t versus frequency including the effects of input voltage is given in figure 3. as the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see efficiency considerations). the complete expression for operating frequency is given by: maximum output current (a) 0 r sense ( w ) 0.12 0.16 0.20 4 ltc1159 ?f02 0.08 0.04 0 1 2 3 5 0.10 0.14 0.18 0.06 0.02 figure 2. r sense vs maximum output current
8 ltc1159/ltc1159-3.3/ltc1159-5 applicatio s i for atio w uu u inductance collapses abruptly when the peak design cur- rent is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple which can cause burst mode operation to be falsely triggered in the ltc1159. do not allow the core to saturate! molypermalloy (from magnetics, inc.) is a low loss core material for toroids, but it is more expensive than ferrite. a reasonable compromise from the same manufacturer is kool m m . toroids are very space efficient, especially when you can use several layers of wire. because they generally lack a bobbin, mounting is more difficult. however, new surface mount designs available from coiltronics do not increase the height significantly. power mosfet selection two external power mosfets must be selected for use with the ltc1159: a p-channel mosfet for the main switch and an n-channel mosfet for the synchronous switch. the peak-to-peak drive levels are set by the v cc voltage on the ltc1159. this voltage is typically 4.5v during start-up and 5v to 7v during normal operation (see extv cc pin connection). consequently, logic-level threshold mosfets must be used in most ltc1159 family applica- tions . the only exception is applications in which extv cc is powered from an external supply greater than 8v, in which standard threshold mosfets (v gs(th) < 4v) may be used. pay close attention to the bv dss specification for the mosfets as well; many of the logic-level mosfets are limited to 30v. selection criteria for the power mosfets include the on resistance r ds(on) , reverse transfer capacitance c rss , input voltage, and maximum output current. when the ltc1159 is operating in continuous mode, the duty cycle for the p-channel mosfet is given by: p-ch duty cycle = v out v in n-ch duty cycle = v in v out v in the mosfet dissipations at maximum output current are given by: f = 1 t off ) ) 1 v out v in where t off = 1.3 10 4 c t once the frequency has been set by c t , the inductor l must be chosen to provide no more than 0.025v/r sense of peak-to-peak inductor ripple current. this results in a minimum required inductor value of: l min = 5.1 10 5 r sense c t v reg as the inductor value is increased from the minimum value, the esr requirements for the output capacitor are eased at the expense of efficiency. if too small an inductor is used, the ltc1159 may not enter burst mode operation and efficiency will be severely degraded at low currents. inductor core selection once the minimum value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy, or kool m m ? cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on the inductance selected. as induc- tance increases, core losses go down but copper (i 2 r) losses will increase. ferrite designs have very low core loss, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that frequency (khz) 0 0 c t capacitance (pf) 200 400 600 1400 1000 50 100 1200 800 150 200 250 v out = 5v v in = 48v v in = 12v v in = 24v ltc1159 ?f03 figure 3. timing capacitor selection kool m m is a registered trademark of magnetics, inc.
9 ltc1159/ltc1159 - 3. 3/ltc1159 - 5 applicatio s i for atio w uu u n-ch p d = v in v out v in (i max ) 2 (1 + ? n ) r ds(on) p-ch p d = v out v in (i max ) 2 (1 + ? p ) r ds(on) + k(v in ) 2 (i max ) (c rss ) (f) where ? is the temperature dependency of r ds(on) and k is a constant inversely related to the gate drive current. both mosfets have i 2 r losses while the p-channel equation includes an additional term for transition losses, which are highest at high input voltages. for v in < 20v the high current efficiency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c rss actually provides higher effi- ciency. the n-channel mosfet losses are the greatest at high input voltage or during a short circuit when the n- channel duty cycle is nearly 100%. the term (1 + ? ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but ? = 0.007/ c can be used as an approximation for low voltage mosfets. c rss is usually specified in the mosfet electrical characteristics. the constant k = 5 can be used for the ltc1159 to estimate the relative contributions of the two terms in the p-channel dissipation equation. the schottky diode d1 shown in figure 1 only conducts during the dead time between the conduction of the two power mosfets. d1 prevents the body diode of the n-channel mosfet from turning on and storing charge during the dead time, which could cost as much as 1% in efficiency (although there are no other harmful effects if d1 is omitted). therefore, d1 should be selected for a forward voltage of less than 0.6v when conducting i max . c in and c out selection in continuous mode, the source current of the p-channel mosfet is a square wave of duty cycle v out /v in . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: c in required i rms ? i max [v out (v in v out )] 1/2 v in this formula has a maximum at v in = 2v out , where i rms = i max /2. this simple worst case condition is com- monly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. an additional 0.1 m f ceramic capacitor may also be required on v in for high frequency decoupling. the selection of c out is driven by the required effective series resistance (esr). the esr of c out must be less than twice the value of r sense for proper operation of the ltc1159: c out required esr < 2r sense optimum efficiency is obtained by making the esr equal to r sense . manufacturers such as nichicon, chemicon, and sprague should be considered for high performance ca- pacitors. the os-con semiconductor dielectric capacitor available from sanyo has the lowest esr for its size at a somewhat higher price. once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple(p-p) requirement. in surface mount applications multiple capacitors may have to be paralleled to meet the capacitance, esr, or rms current handling requirements of the application. alumi- num electrolytic and dry tantalum capacitors are both available in surface mount configurations. in the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. an excellent choice is the avx tps series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. for example, if 200 m f/10v is called for in an application requiring 3mm height, two avx 100 m f/10v (p/n tpsd107k010) could be used. consult the manufacturer for other specific recom- mendations. at low supply voltages, a minimum value of c out is suggested to prevent an abnormal low frequency oper- ating mode (see figure 4). when c out is too small, the output ripple at low frequencies will be large enough to trip the voltage comparator. this causes the burst mode operation to be activated when the ltc1159 would normally be in continuous operation. the effect is most
10 ltc1159/ltc1159-3.3/ltc1159-5 applicatio s i for atio w uu u figure 4. minimum suggested c out (v in ?v out ) voltage (v) 0 c out ( m f) 600 800 1000 4 ltc1159 ?tpc04 400 200 0 1 2 3 5 l = 50 m h r sense = 0.02 w l = 25 m h r sense = 0.02 w l = 50 m h r sense = 0.05 w pronounced with low values of r sense and can be improved by operating at higher frequencies with lower values of l. the output remains in regulation at all times. load transient response switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to d i load esr, where esr is the effective series resistance of c out . d i load also begins to charge or discharge c out until the regulator loop adapts to the current change and returns v out to its steady state value. during this recovery time v out can be monitored for overshoot or ringing which would indicate a stability problem. the i th external components shown in the figure 1 circuit will provide adequate compensation for most applications. a second, more severe transient is caused by switching in loads with large (>1 m f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately 25 c load . thus a 10 m f capacitor would require a 250 m s rise time, limiting the charging current to about 200ma. line transient response the ltc1159 has better than 60db line rejection and is generally impervious to large positive or negative line voltage transients. however, one rarely occurring condi- tion can cause the output voltage to overshoot if the proper precautions are not observed. this condition is a negative v in transition of several volts followed within 100 m s by a positive transition of greater than 0.5v/ m s slew rate. the reason this condition rarely occurs is because it takes tens of amps to slew the regulator input capacitor at this rate! the solution is to add a diode between the cap and v in pins of the ltc1159 as shown in several of the typical application circuits. if you think your system could have this problem, add the diode. note that in surface mount applications it can be combined with the p-gate diode by using a low cost common cathode dual diode. extv cc pin connection the ltc1159 contains an internal pnp switch connected between the extv cc and v cc pins. the switch closes and supplies the v cc power whenever the extv cc pin is higher in voltage than the 4.5v internal regulator. this allows the mosfet driver and control power to be derived from the output during normal operation and from the internal regulator when the output is out of regulation (start-up, short circuit). significant efficiency gains can be realized by powering v cc from the output, since the v in current resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(efficiency). for 5v regulators this simply means connecting the extv cc pin directly to v out . how- ever, for 3.3v and other low voltage regulators, additional circuitry is required to derive v cc power from the output. the following list summarizes the four possible connec- tions for extv cc : 1. extv cc left open. this will cause v cc to be powered only from the internal 4.5v regulator resulting in re- duced mosfet gate drive levels and an efficiency pen- alty of up to 10% at high input voltages.
11 ltc1159/ltc1159 - 3. 3/ltc1159 - 5 applicatio s i for atio w uu u 2. extv cc connected directly to v out . this is the normal connection for a 5v regulator and provides the highest efficiency. 3. extv cc connected to an output-derived boost net- work. for 3.3v and other low voltage regulators, effi- ciency gains can still be realized by connecting extv cc to an output-derived voltage which has been boosted to greater than 4.5v. this can be done either with the inductive boost winding shown in figure 5a or the capacitive charge pump shown in figure 5b. the charge pump has the advantage of simple magnetics and gen- erally provides the highest efficiency at the expense of a slightly higher parts count. 4. extv cc connected to an external supply. if an external supply is available in the 5v to 12v range, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. there are no restric- tions on the extv cc voltage relative to v in . extv cc may be higher than v in providing extv cc does not exceed the 15v absolute maximum rating. when driving standard threshold mosfets, the exter- nal supply must always be present during operation to prevent mosfet failure due to insufficient gate drive . the ltc1149 family should also be considered for applications which require the use of standard threshold mosfets. important information about ltc1159 adjustable applications when an output voltage other than 3.3v or 5v is required, the ltc1159 adjustable version is used with an external resistive divider from v out to the v fb pin (figure 6). the regulated voltage is determined by: v out = 1.25v ) ) 1 + r2 r1 the v fb pin is extremely sensitive to pickup from the inductor switching node . care should be taken to isolate the feedback network from the inductor, and the 100pf capacitor should be connected between the v fb and s-gnd pins next to the package. in ltc1159n and ltc1159s applications with v out > 5.5v, the v cc pin may self-power through the sense pins when shdn2 is taken high, preventing shutdown. in these applications, a pull-down must be added to the sense C pin as shown in figure 6. this pull-down effectively takes the place of the shdn1 pin, ensuring complete shutdown. note: for versions in which both the shdn1 and shdn2 pins are available (ltc1159g and all fixed output ver- sions), the two pins are simply connected to each other and driven together to guarantee complete shutdown. the figure 6 circuit cannot be used to regulate a v out which is greater than the maximum voltage allowed on the ltc1159 sense pins (13v). in applications with v out > 13v, r sense must be moved to the ground side of the output capacitor and load. this operates the current sense v in p-drive ltc1159-3.3 p-gate n-ch v in 1n4148 p-ch + + + c in r sense c out 1 m f v out ltc1159 ?f05a n-gate p-gnd extv cc l 1:1 figure 5a. inductive boost circuit for extv cc figure 5b. capacitive charge pump for extv cc v in p-drive ltc1159-3.3 p-gate n-ch bat85 0.22 m f 1 m f bat85 bat85 vn2222ll v in p-ch + c in r sense + c out + v out ltc1159 ?f05b n-gate p-gnd extv cc l
12 ltc1159/ltc1159-3.3/ltc1159-5 applicatio s i for atio w uu u figure 6. high efficiency adjustable regulator with 5.5v < v out < 13v 0.15 m f v in cap p-drive p-gnd extv cc v fb ltc1159 i th c t p-gate v cc v cc shdn2 sense sense + irfz34 vn2222ll 0.1 m f 100pf 5m 1n4148 v in irf9z34 1n5819 0.01 m f 100 w 100 w + 100 m f 50v + 150 m f 16v os-con + 1 m f 0v = normal >3v = shutdown 3300pf c t 390pf 1k n-gate s-gnd v out r1 24.9k ltc1159 ?f06 r2 215k v out = () 1 + r2 r1 values shown for v out = 12v/2.5a 100 m h r sense 0.039 w 1.25 comparator at 0v common mode, increasing the off-time approximately 40% and requiring the use of a smaller timing capacitor c t . inverting regular applications the ltc1159 can also be used to obtain negative output voltages from positive inputs. in these inverting applica- tions, the current sense resistor connects to ground while the ltc1159 and n-channel mosfet connections, which would normally go to ground, instead ride on the negative output. this allows the negative output voltage to be set by the same process as in conventional applications, using either the internal divider (ltc1159-3.3, ltc1159-5) or an external divider with the adjustable version. figure 15 in the typical applications shows a synchronous 12v to C12v converter which can supply up to 1a with better than 85% efficiency. by grounding the extv cc pin in the figure 15 circuit, the entire 12v output voltage is placed across the driver and control circuits since the ltc1159 ground pins are at C12v. during start-up or short-circuit conditions, operating power is supplied by the internal 4.5v regulator. the shutdown signal is level-shifted to the negative output rail by q3, and q4 ensures that q1 and q2 remain off during the entire shutdown sequence. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100 C (l1 + l2 + l3 + ...) where l1, l2, etc., are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc1159 circuits: 1) ltc1159 v in current, 2) ltc1159 v cc current, 3) i 2 r losses, and 4) p-channel transition losses. 1. ltc1159 v in current is the dc supply current given in the electrical characteristics which excludes mosfet driver and control currents. v in current results in a small (< 1%) loss which increases with v in . 2. ltc1159 v cc current is the sum of the mosfet driver and control circuit currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from
13 ltc1159/ltc1159 - 3. 3/ltc1159 - 5 applicatio s i for atio w uu u ltc1159 sense + sense 9 8 1000pf r1 100 w r2 100 w l r sense + c out r3 ltc1159 ?f07 figure 7. suppressing burst mode operation low to high to low again, a packet of charge dq moves from v cc to ground. the resulting dq/dt is a current out of v cc which is typically much larger than the control circuit current. in continuous mode, i gatechg ? f (q p + q n ), where q p and q n are the gate charges of the two mosfets. by powering extv cc from an output-derived source, the additional v in current resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(efficiency). for example in a 20v to 5v application, 10ma of v cc current results in approxi- mately 3ma of v in current. this reduces the mid-current loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are easily predicted from the dc resistances of the mosfet, inductor, and current shunt. in con- tinuous mode all of the output current flows through l and r sense , but is chopped between the p-channel and n-channel mosfets. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resis- tances of l and r sense to obtain i 2 r losses. for example, if each r ds(on) = 0.1 w , r l = 0.15 w , and r sense = 0.05 w , then the total resistance is 0.3 w . this results in losses ranging from 3% to 12% as the output current increases from 0.5a to 2a. i 2 r losses cause the efficiency to roll-off at high output currents. 4. transition losses apply only to the p-channel mosfet, and only when operating at high input voltages (typi- cally 20v or greater). transition losses can be esti- mated from: transition loss ? 5(v in ) 2 (i max )(c rss )(f) other losses including c in and c out esr dissipative losses, schottky conduction losses during dead time, and inductor core losses, generally account for less than 2% total additional loss. auxiliary windings C suppressing burst mode operation the ltc1159 synchronous switch removes the normal limitation that power must be drawn from the inductor primary winding in order to extract power from auxiliary windings. with synchronous switching, auxiliary out- puts may be loaded without regard to the primary output load, providing that the loop remains in continuous mode operation. burst mode operation can be suppressed at low output currents with a simple external network which cancels the 0.025v minimum current comparator threshold. this tech- nique is also useful for eliminating audible noise from certain types of inductors in high current (i out > 5a) applications when they are lightly loaded. an external offset is put in series with the sense C pin to subtract from the built-in 0.025v offset. an example of this technique is shown in figure 7. two 100 w resistors are inserted in series with the leads from the sense resistor. with the addition of r3, a current is generated through r1 causing an offset of: v offset = v out ) ) r1 r1 + r3 if v offset > 0.025v, the minimum threshold will be cancelled and burst mode operation is prevented from occurring. since v offset is constant, the maximum load current is also decreased by the same offset. thus, to get back to the same i max , the value of the sense resistor must be reduced: r sense ? m w 75 i max to prevent noise spikes from erroneously tripping the current comparator, a 1000pf capacitor is needed across the sense C and sense + pins.
14 ltc1159/ltc1159-3.3/ltc1159-5 applicatio s i for atio w uu u board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc1159. these items are also illustrated graphically in the layout diagram of figure 8. check the following in your layout: 1) are the signal and power grounds segregated? the ltc1159 signal ground must connect separately to the (C) plate of c out . the other ground pin(s) should return to the source of the n-channel mosfet, anode of the schottky diode, and (C) plate of c in , which should have as short lead lengths as possible. 2) does the ltc1159 sense C pin connect to a point close to r sense and the (+) plate of c out ? in adjustable applications, the resistive divider r1, r2 must be con- nected between the (+) plate of c out and signal ground. 3 ) are the sense C and sense + leads routed together with minimum pc trace spacing? the differential decoupling capacitor between the two sense pins should be as close as possible to the ltc1159. up to 100 w may be placed in series with each sense lead to help decouple the sense pins. however, when these resistors are used, the capacitor should be no larger than 1000pf. 4) does the (+) plate of c in connect to the source of the p-channel mosfet as closely as possible? an addi- tional 0.1 m f ceramic capacitor between v in and power ground may be required in some applications. 5) is the v cc decoupling capacitor connected closely be- tween the v cc pins of the ltc1159 and power ground? this capacitor carries the mosfet driver peak currents. 6) in adjustable versions, the feedback pin is very sensitive to pickup from the switch node. care must be taken to isolate v fb from possible capacitive coupling of the inductor switch signal. 7) is the shdn1 pin actively pulled to ground during normal operation? shdn1 is a high impedance pin and must not be allowed to float. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 p-gate v in v cc p-drive v cc c t i th sense cap shdn2 extv cc n-gate p-gnd s-gnd sense + c out d1 p-channel 1k 3300pf c t r1 r2 r sense n-channel c in l + + v out v in output divider required with adjustable version only bold lines indicate high current paths ltc1159 ?f08 1000pf 100pf + + 1 m f 0.15 m f 1n4148 shutdown 5v extv cc connection + 0.1 m f v fb (shdn1) figure 8. ltc1159 layout diagram (n and s packages)
15 ltc1159/ltc1159 - 3. 3/ltc1159 - 5 figure 10. high efficiency 8v to 20v input 2.5/5a output regulator p-gate v in v cc p-drive v cc c t i th sense cap shdn2 extv cc n-gate p-gnd s-gnd v fb sense + 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc1159 0.15 m f shutdown 0.1 m f 1n4148 1n4148 + 1000pf 2k 10k 10k 1% 0.047 m f 3.3 m f 1000pf 100pf 100 w 100 w irf7201 irf7201 mbrs330 1 m f wima + 47 m f 25v 2 os-con v in 8v to 20v 5v l* 15 m h r sense ** 0.02 w + 330 m f 6.3v 3 avx ltc1159 ?f10 v out 2.5v/5a *magnetics 77120-a7 core, 16t 18ga. wire **krl sl-1-r020j irf7205 10k 1% 3.3v 0v (a) continuous mode operation 3.3v 0v (b) burst mode operation ltc1159 ?f09 figure 9. c t pin 6 waveforms troubleshooting hints since efficiency is critical to ltc1159 applications it is very important to verify that the circuit is functioning correctly in both continuous and burst mode operation. the wave- form to monitor is the voltage on the c t pin . in continuous mode (i load > i burst ) the voltage should be a sawtooth with a 0.9v p-p swing. this voltage should never dip below 2v as shown in figure 9a. when the load current is low (i load < i burst ), burst mode operation should occur with the c t waveform periodically falling to ground as shown in figure 9b. if the c t pin is observed falling to ground at high output currents, it indicates poor decoupling or improper ground- ing. refer to the board layout checklist. typical applicatio s u applicatio n s i n for m atio n wu u u
16 ltc1159/ltc1159-3.3/ltc1159-5 typical applicatio s u figure 12. high current, high efficiency 15v to 40v input 5v/10a output regulator p-gate v in v cc p-drive v cc c t i th sense cap shdn2 extv cc n-gate p-gnd s-gnd shdn1 sense + 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc1159-5 0.15 m f 0.33 m f 0.1 m f 1n4148 1n4148 + 750pf 470 w 100 w 100 w 18k 0.047 m f 10 m f 1000pf shutdown mtp75n05hd mbr350 1 m f wima + 1200 m f 50v 2 lxf v in 15v to 40v 12v l* 22 m h r sense ** 0.01 w + 220 m f 10v 3 os-con ltc1159 ?f12 v out 5v/10a *hurricane lab hl-kk122t/bb **dale lvr-3-0.01 smp40p06 heat sink mpsa56 mpsa06 mpsa56 1n4148 figure 11. 5:1 input range (4v to 20v) high efficiency 3.3v/2.5a regulator p-gate v in v cc p-drive v cc c t i th sense cap shdn2 extv cc n-gate p-gnd s-gnd shdn1 sense + 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc1159-3.3 0.15 m f 0.1 m f 1n4148 1n4148 + 270pf 1k 3300pf 1 m f 0.01 m f 1 m f shutdown si9410dy mbrs130lt3 0.1 m f + 47 m f 25v os-con v in 4v to 20v l* 20 m h r sense ** 0.04 w + + 330 m f 6.3v 2 avx ltc1159 ?f11 v out 3.3v/2.5a *coiltronics ctx20-4 **krl sl-1/2-r040j si9435dy vn2222ll bat85 bat85 bat85 0.22 m f
17 ltc1159/ltc1159 - 3. 3/ltc1159 - 5 typical applicatio s u figure 14. 17w dual output high efficiency 5v and 3.3v regulator p-gate v in v cc p-drive v cc c t i th sense cap shdn2 extv cc n-gate p-gnd s-gnd v fb sense + 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc1159 0.33 m f 0v = normal >2v = shutdown 0.22 m f bas16 bas16 + 1000pf 1000pf 1k 24.9k 1% 100k 220 m f 10v 4 avx 3.3v output 5v output r sense ** 0.02 w 2200pf 2.2 m f + 10 m f bas16 56pf 0.01 m f 1 m f bas16 bas16 t* si9410dy si9410dy si9435dy si9435dy mbrs140t3 1 m f wima + 47 m f 25v 2 os-con v in 5.5v to 24v + ltc1159 ?f14 *hurricane lab hl-8700 **krl sl-1-r020j 124k 1% 100 w 100 w 102k 1% 1k + 220 m f 10v 2 avx + figure 13. high efficiency 15v to 40v input 12v/5a output regulator p-gate v in v cc p-drive v cc c t i th sense cap shdn2 extv cc n-gate p-gnd s-gnd v fb sense + 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc1159 0.15 m f 0.1 m f 1n4148 1n4148 + 390pf 470 w 10.5k 1% 5m 3300pf 3.3 m f 1000pf 0v = normal >3v = shutdown vn2222ll 100pf 100 w 100 w irfz44 mbr350 1 m f wima + 100 m f 63v 2 sxc v in 15v to 40v l* 50 m h r sense ** 0.02 w + 150 m f 16v 2 os-con ltc1159 ?f13 v out 12v/5a *coiltronics ctx50-5-km **irc lo-3-0.02 5% irf9z34 heat sink 90.9k 1%
18 ltc1159/ltc1159-3.3/ltc1159-5 typical applicatio s u 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 p-gate v in v cc p-drive v cc c t i th sense cap shdn2 extv cc n-gate p-gnd s-gnd sense + 100 w 100 w 0.15 m f v fb (shdn1) + + ltc1159 0.1 m f 1n4148 mbrs140 200pf 10.5k 90.5k q4 2n7002 150 m f 16v ? 2 os-con 1k 6800pf 5.1v 1n5993 1n5818 c t 390pf r sense ** 0.05 w 1000pf q1 si9435 q2 si9410 v in 12v +30% ?0% 0.1 m f 330 m f 35v nichicon l* 100 m h output ?2v/1a 20k 510k q3 tp0610l shutdown 5v or 3.3v 3.3 m f + dale tj4-100-1 m irc lr2512-01-r050-j * ** figure 15. high efficiency 12v to C12v 1a converter
19 ltc1159/ltc1159 - 3. 3/ltc1159 - 5 dimensions in inches (millimeters) unless otherwise noted. information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package descriptio n u g package 20-lead plastic ssop n16 0694 0.255 0.015* (6.477 0.381) 0.770* (19.558) max 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0.015 (0.381) min 0.125 (3.175) min 0.130 0.005 (3.302 0.127) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.018 0.003 (0.457 0.076) 0.045 0.015 (1.143 0.381) 0.100 0.010 (2.540 0.254) 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.025 0.015 +0.635 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protursions shall not exceed 0.010 inch (0.254mm). 20ssop 0694 0.005 ?0.009 (0.13 ?0.22) 0 ?8 0.022 ?0.037 (0.55 ?0.95) 0.205 ?0.212* (5.20 ?5.38) 0.301 ?0.311 (7.65 ?7.90) 1234 5 6 7 8910 0.278 ?0.289* (7.07 ?7.33) 17 18 14 13 12 11 15 16 19 20 0.068 ?0.078 (1.73 ?1.99) 0.002 ?0.008 (0.05 ?0.21) 0.0256 (0.65) bsc 0.010 ?0.015 (0.25 ?0.38) *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.006 inch (0.15mm). n package 16-lead plastic dip
20 ltc1159/ltc1159-3.3/ltc1159-5 part number description comments ltc1142 dual high efficiency synchronous step-down switching regulator dual version of ltc1148 ltc1143 dual high efficiency step-down switching regulator controller dual version of ltc1147 ltc1147 high efficiency step-down switching regulator controller nonsynchronous, 8-lead, v in 16v ltc1148 high efficiency step-down switching regulator controller synchronous, v in 20v ltc1149 high efficiency step-down switching regulator synchronous, v in 48v, for standard threshold fets ltc1174 high efficiency step-down and inverting dc/dc converter 0.5a switch, v in 18.5v, comparator ltc1265 high efficiency step-down dc/dc converter 1.2a switch, v in 13v, comparator ltc1267 dual high efficiency synchronous step-down switching regulators dual version of ltc1159 dimensions in inches (millimeters) unless otherwise noted. package descriptio n u ? linear technology corporation 1994 lt/gp 1294 10k ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7487 (408) 432-1900 l fax : (408) 434-0507 l telex : 499-3977 s package 16-lead plastic soic 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0??8?typ 0.008 ?0.010 (0.203 ?0.254) 1 2 3 4 5 6 7 8 0.150 ?0.157* (3.810 ?3.988) 16 15 14 13 0.386 ?0.394* (9.804 ?10.008) 0.228 ?0.244 (5.791 ?6.197) 12 11 10 9 so16 0893 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) typ *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.006 inch (0.15mm). related parts

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